The present invention is related to a method for measuring the bias voltage, and more particularly, to a method for measuring the bias voltage of the sense amplifier in a memory device.
The memory device is the place where the programs and the information are temporarily saved in a computer. Generally speaking, the memory device is divided into two types, the read-only memory (ROM) and the random access memory (RAM). The RAM is the place for saving the operating system and application program. Basically, all programs must loaded into RAM to run correctly. The RAM is divided into two types, the dynamic random access memory (DRAM) and the static random access memory (SRAM). The basic structure of DRAM uses two electrical elements including a transistor and a capacitor to form a memory cell module. The information of one bit is saved according to the charged status of the capacitor in the memory cell module. However, the capacitor in DRAM structure will be discharged automatically. Therefore, an extra circuit is designed for regularly examining the voltage of the capacitor so that the capacitor can be charged or discharged to prevent from losing information. This is what we call xe2x80x9cmemory refresh.xe2x80x9d Because the DRAM has to proceed with the memory refresh continuously, it is called xe2x80x9cdynamicxe2x80x9d random access memory.
In fact, the DRAM unit is a series connection of a simple transistor and a capacitor. The capacitor is used for saving the electric charge which represents the information. The transistor is used for controlling the access mechanism of internal electric charge in the capacitance. Please refer to FIG. 1. FIG. 1 is a diagram illustrating the structure of the DRAM unit according to the prior art. Take N channel as an example, the method which DRAM records and reads the internal information is described as following:
1. writing xe2x80x9c1xe2x80x9d signal:
When writing xe2x80x9c1xe2x80x9d into the DRAM, a positive bias voltage is applied to the plate 3 of the capacitor 1 to make the semiconductor 6 surface layer beneath the capacitor 1 reverse polarity thereof. Meantime, the positive bias voltage is applied to both the word line (WL) 4 and bit line (BL) 5 under the circumstance that the transistor 2 (it is also a metal-oxide semiconductor (MOS)) is electrically conducted. The electric charges of the reverse layer formed because of the polarity reversion in the capacitor 1 flow to the bit line (BL) 5 then and leave the electric charges of the empty layer beneath the capacitor 1. The signal saved in the DRAM unit now is called xe2x80x9c1.xe2x80x9d
After xe2x80x9c1xe2x80x9d is written, the capacitor 1 is under a heat-unbalanced status. This is because the location beneath capacitor 1 is under the polarity reversion status without the reverse layer, which causes a heat-unbalanced situation. At this time, any electron formed by every kinds of energies from outside might try flowing to this area and try reaching the heat-balanced status, which will result in the damage of the signal saved in the capacitor 1. Therefore, the memory refresh must be proceeded regularly in the DRAM unit to keep the signal of the electrical charge. This is why it is called xe2x80x9cdynamic.xe2x80x9d
2. writing xe2x80x9c0xe2x80x9d signal:
While the capacitor 1 is under the heat-balanced status, the memory refresh proceeded when writing xe2x80x9c1xe2x80x9d into DRAM needs not to proceeded. In other words, the memory refresh in the DRAM is mainly used for maintaining the xe2x80x9c1xe2x80x9d signal.
3. Reading xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d signals
When reading the signal saved in the memory cell, the bit line (BL) will be switched to a comparator circuit. The word line (WL) will be then accept the positive bias voltage so that the signal saved in the capacitor 1 can connect with the BL directly. The signal of BL will be compared with a reference voltage through the comparator circuit and the purpose of judging the saved information will be achieved. Apparently, when xe2x80x9c1xe2x80x9d signal is read, it means the electric potential at BL is larger than the reference voltage. On the contrary, when xe2x80x9c0xe2x80x9d signal is read, it means the electric potential at BL is smaller than the reference voltage.
From the above description, the capacitor is known as the main storage in a DRAM unit. The larger capacitor a DRAM has, the longer period it needs for refreshing memory regularly. Besides, the larger capacitor a DRAM has, the harder that the storage information is interfered by the outside. However, the storage status in the capacitor is controlled by the change of the bias voltage. It is therefore that how to control the input bias voltage effectively has become the main purpose of the present invention. Thus, a method for measuring the bias voltage in a memory device is provided to control the bias voltage effectively.
The main purpose of the present invention is to provide a method for measuring the bias voltage of the sense amplifier in a memory device.
It is another object of the present invention to provide a method for measuring the bias voltage of the sense amplifier in a memory device. Through measuring the bias voltage, the bias voltage can be adjusted in good time so that an ideal output voltage can be obtained.
It is another object of the present invention to provide a method for measuring the bias voltage of the sense amplifier in a memory device. Through measuring the bias voltage, the accurate bias voltage can be obtained without wasting time and manpower.
According to an aspect of the present invention, the method for measuring the bias voltage of the sense amplifier in a memory device, wherein each of the plural sense amplifiers is electrically connected with a memory cell module, comprises the steps of: selecting the plural sense amplifiers as a measurement area, writing a midlevel voltage into the respective memory cell modules connected to the plural the sense amplifiers respectively, providing a reference voltage of the midlevel voltage into the plural sense amplifiers in the measurement area, recording output signals of the plural sense amplifiers, wherein the output signal is valued one of xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d, counting numbers of xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d, and obtaining a ratio of the number of xe2x80x9c0xe2x80x9d over the number of xe2x80x9c1xe2x80x9d, and obtaining the bias voltage of the plural sense amplifiers in the measurement area as the ratio.
In accordance with the present invention, the memory device is a dynamic random access memory (DRAM).
Preferably, the midlevel voltage is an average voltage of a low input voltage VSS and a high input voltage VDD.
Preferably, the reference voltage is an average voltage of a low input voltage VSS and a high input voltage VDD.
Preferably, the ratio bigger than 0.5 represents that a biased level of the measurement area is too much close to the low input voltage VDD.
Preferably, the ratio lower than 0.5 represents that a biased level of the measurement area is too much close to the high input voltage VSS.
According to another aspect of the present invention, a method for measuring a bias voltage of a sense amplifier in a memory device, wherein the sense amplifier is electrically connected with a memory cell module, comprises the steps of: providing a reference voltage, writing a first voltage series starting from a high voltage to a low voltage into the memory cell module, reading output signals, being one of xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d, of the sense amplifier in sequence in response to the first voltage series, recording an input voltage of the first voltage series as a third voltage when the output signal change from the xe2x80x9c1xe2x80x9d to the xe2x80x9c0xe2x80x9d, writing a second voltage series starting from a low voltage to a high voltage into the memory cell module, reading output signals, being one of xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d, of the sense amplifier in sequence in response to the second voltage series, recording an input voltage of the second voltage series as a fourth voltage when the output signal change from the xe2x80x9c0xe2x80x9d to the xe2x80x9c1xe2x80x9d, and taking an average of the third voltage and the fourth voltage as a bias voltage for the sense amplifier.
In accordance with the present invention, the memory device is included in a dynamic random access memory (DRAM).
Preferably, the reference voltage is an average voltage of a low input voltage VSS and a high input voltage VDD.
Preferably, the first voltage series is permuted according to an equal difference.
Preferably, the second voltage series is permuted according to an equal difference.
Preferably, the first voltage series and the second voltage series are both permuted with an equal difference and have the same equal difference.
The foregoing and other features and advantages of the present invention will be more clearly understood through the following descriptions with reference to the drawings, wherein: